The invention will be described in detail in the context of DRAMs, although it is equally applicable to SRAMs.
Bit line decoders (sometimes referred to as Y decoders) typically have several (e.g. 3 or 4) inputs, each of which is chosen from a group of plural decoded addresses (e.g. 4). Normally only one signal in each group of four would be "1" at any time.
Referring to FIG. 1, each of a group of Y decoders, shown as NAND gates 2, have their outputs connected to the gates of a pair of access field effect transistors 4, for enabling connection of bit lines such as BL0, /BL0, BL1 and /BL1 to data bus lines DB0, /DB0, DB1 and /DB1 respectively output via sense amplifiers 6. The inputs of NAND gates 2 are connected to different predecoder lines 8 of predecoder buses. The lines of the predecoder buses are connected to the outputs of predecoders, in the embodiment shown being the outputs of groups of gates 10A and 10B.
The inputs of the group of gates 10A are connected to a source of Y address signals, Yi and Y(i+1), and the inputs of the group of gates 10B are connected to a source of Y address signal, Y(i+2), Y(i+3). The sources of address signals are input pins to the DRAM.
In a typical memory array consisting of 2.sup.10 (1024) bit lines, where four bits of data are accessed simultaneously via four differential databuses, 2.sup.8 (256) Y-decoders each consisting of four input gates, each input chosen from a group of four predecoded addresses, would determine which four bitlines to connect to the databus. The Y-decoders themselves could be implemented as NAND or NOR gates through the application of deMorgan's theorem.
In operation, normally only one signal on each of the predecoder lines 8 is "1" at a time, whereby a single decoder is enabled. This limits the ability of the DRAM to provide a block write to plural DRAM cells, with variable and selectable size of the block of cells to be written. Large block writes are accomplished by sequentially writing to groups of bitlines addressed by one Y-decoder. In applications such as computer graphics, where large fields of memory are written with the same value, the speed of block writes implemented sequentially can seriously degrade performance.
Standard video random access memory (VRAM) includes a block write feature, but it is only for a fixed sized block of four or eight addresses. Larger blocks would still require a slow, sequential operation.
A truth table of Y address input and predecoder line logic level is as follows:
TABLE A ______________________________________ Y Address Precoder One Logic Level Yi Yi + i = Yj Yij(0) Yij(1) Yij(2) Yij(3) ______________________________________ 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 1 0 1 1 0 0 0 1 ______________________________________